Program-controlled unit

ABSTRACT

A program-controlled unit has debug resources for monitoring the operations proceeding within the program-controlled unit. The program-controlled unit described is distinguished by the fact that the debug resources contain a CPU, and/or that a portion of the debug resources is provided for monitoring the operations proceeding within the remainder of the debug resources. Debug resources constructed in this way make it possible for errors occurring in program-controlled units to be localized and eliminated rapidly and simply under all circumstances.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a program-controlled unit havingdebug resources for monitoring the operations proceeding within theprogram-controlled unit.

[0003] Program-controlled units such as microprocessors,microcontrollers, signal processors, etc. are known in innumerableembodiments and do not require more detailed explanation.

[0004] A known problem of program-controlled units is that it is oftennot possible or not readily possible to localize and eliminate errorsthat occur.

[0005] For this reason, there has been a changeover to equippingprogram-controlled units with debug resources that can monitor theoperations proceeding within the program-controlled unit. The debugresources include, for example, prior-art on-chip debug support modulesand OCDS modules.

[0006] Such and other debug resources make it possible to monitor theoccurrence of states or events within the program-controlled unit, whichstates or events can be prescribed from outside the program-controlledunit, and, when such a state or such an event has occurred, to carry outor instigate actions which can be prescribed from outside theprogram-controlled unit.

[0007] The states or events whose occurrence can be monitored by thedebug resources include, but are not limited to, the following:

[0008] the access by the program-controlled unit or specific componentsthereof to specific memory addresses or registers, and/or

[0009] the transfer of specific data within the program-controlled unit,and/or

[0010] the position of the instruction pointer.

[0011] The actions that the debug resources execute or instigate whensuch a state or other state or event occurs may include but are notlimited to:

[0012] reporting of the fact that the condition to be monitored hasoccurred, to a device provided outside the program-controlled unit,

[0013] the read-out or the alteration of the content of specific memoryelements or registers,

[0014] the outputting of trace information, i.e. the outputting ofaddresses, data and/or control signals that are used or transferredwithin the program-controlled unit, to a device provided outside theprogram-controlled unit,

[0015] the stopping of the program execution,

[0016] the continuation of the program execution in the so-calledsingle-step mode, or

[0017] the execution of routines serving for the debugging or emulationof the program-controlled unit by the CPU of the program-controlledunit.

[0018] The provision of debug resources thus affords a whole host ofpossibilities for localizing and eliminating errors occurring in theprogram-controlled unit.

[0019] However, the possibilities afforded by the debug resources dependon the logic forming the debug resources. Therefore, when planning thislogic, it is necessary to carefully weigh what functions the debugresources should or must be able to perform, and what they should orneed not. Both debug resources with a functional scope that isrestricted to an excessively great extent, and debug resources with anexcessively large functional scope are disadvantageous. The formerbecause this means that only simple errors can be found or the debuggingis associated with a high outlay, and the latter because this increasesthe risk of the debug resources themselves not operating properly onaccount of incorrect operation and/or hardware faults.

SUMMARY OF THE INVENTION

[0020] It is accordingly an object of the invention to provide aprogram-controlled unit that overcomes the hereinafore-mentioneddisadvantages of the heretofore-known devices of this general type andthat has debug resources that can localize and eliminate errorsoccurring under all circumstances rapidly and simply.

[0021] With the foregoing and other objects in view, there is provided,in accordance with the invention, a program-controlled unit. The programcontrolled unit includes debug resources such as a CPU. The debugresources monitor operations proceeding within the program-controlledunit.

[0022] The program-controlled units according to the invention aredistinguished by the following features:

[0023] that the debug resources contain a CPU, and/or

[0024] that a portion of the debug resources is provided for monitoringthe operations proceeding within the remainder of the debug resources.

[0025] By virtue of the fact that the debug resources contain a CPU,they can execute arbitrarily complex monitoring processes and actions.This is not possible in the case of conventional debug resources, i.e.debug resources constructed using logic, even when a very complex logicis involved. The debug resources constructed using a CPU can, at thesame time, even be realized smaller and be operated more easily thanconventional debug resources with a large functional scope.

[0026] By virtue of the fact that a portion of the debug resources canmonitor the operations proceeding within the remainder of the debugresources, errors occurring within the debug resources can also belocalized and eliminated. Thus, it is no longer a disadvantage or at anyrate a major disadvantage if the debug resources are constructed withgreater complexity than has been the case hitherto.

[0027] The proposed innovations can be used independently of one anotherand make it possible, individually and definitely in combination, forerrors that occur in program-controlled units to be localized andeliminated under all circumstances rapidly and simply.

[0028] Independent of this, it is thereby possible to constructuniversally useable debug resources which do not have to be adapted, oronly have to be slightly adapted, to the program-controlled units inwhich they are used in each case.

[0029] Other features which are considered as characteristic for theinvention are set forth in the appended claims.

[0030] Although the invention is illustrated and described herein asembodied in a program-controlled unit, it is nevertheless not intendedto be limited to the details shown, since various modifications andstructural changes may be made therein without departing from the spiritof the invention and within the scope and range of equivalents of theclaims.

[0031] The construction and method of operation of the invention,however, together with additional objects and advantages thereof will bebest understood from the following description of specific embodimentswhen read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a block diagram of a first program-controlled unit withthe debug resources according to the invention; and

[0033]FIG. 2 is a block diagram of a second program-controlled unit withthe debug resources according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] The program-controlled units described below aremicrocontrollers. However, the special features of the microcontrollerthat are described below can also be used in any otherprogram-controlled units, such as microprocessors, signal processors,and the like.

[0035] For clarity, only the components of the microcontrollers that areof particular interest are shown.

[0036] Referring now to the figures of the drawings in detail and first,particularly to FIG. 1 thereof, there is shown the program-controlledunit containing a first CPU having a reference symbol “CPU”, a firstmemory device MEM, a first I/O controller IO1, a second I/O controllerIO2, a USB controller USB, and debug resources. The debug resourcescontain an OCDS module OCDS, a second CPU DEBCPU, a second memory deviceDEBMEM, and a data acquisition device TRACE.

[0037] The aforementioned components are connected to one another via abus BUS and/or via individual connections as shown in FIG. 1.

[0038] In normal operation of the program-controlled unit, the CPU CPUreads from the memory device MEM instructions and operands storedtherein and executes these in interaction with the I/O controllers IO1,IO2, the USB controller USB and/or other peripheral units contained inthe program-controlled unit.

[0039] The debug resources are inactive in normal operation of theprogram-controlled unit, and are used only during the debugging oremulation of the program-controlled unit.

[0040] The debug resources are controlled by a device provided outsidethe program-controlled unit, which may be a computer, for example. Forthis purpose, the external device is connected via a JTAG interface JTAGor some other interface of the program-controlled unit to the debugresources (in the example considered to the OCDS module OCDS, butpossibly also to one or more other or further components of the debugresources). Via the JTAG interface, the debug resources also outputspecific data to the external device, which can determine therefrom theoperations proceeding in the program-controlled unit.

[0041] The OCDS module OCDS monitors the occurrence of conditions withinthe program-controlled unit, the conditions being prescribed to it bythe external device, and executes actions that are prescribed by theexternal device or fixedly set actions when one or more conditionsoccur.

[0042] In this case, the prescribed conditions whose occurrence ismonitored by the OCDS module OCDS may encompass all conditions which canbe monitored by conventional OCDS modules, and the actions which theOCDS module OCDS executes or instigates in response to the occurrence ofa condition may encompass all actions which can be executed byconventional OCDS modules in such cases.

[0043] Accordingly, the states or events whose occurrence can bemonitored by the OCDS module OCDS may include, but are not limited to,the following:

[0044] the access by the program-controlled unit or specific componentsthereof to specific memory addresses or registers, and/or

[0045] the transfer of specific data within the program-controlled unit,and/or

[0046] the position of the instruction pointer.

[0047] The actions that the OCDS module OCDS executes or instigates whensuch a state or event or other state or event occurs may include, butare not limited to, the following:

[0048] reporting of the fact that the condition to be monitored hasoccurred, to the external device provided outside the program-controlledunit,

[0049] the read-out or the alteration of the content of specific memoryelements or registers,

[0050] the stopping of the program execution by the CPU CPU,

[0051] the continuation of the program execution in the so-calledsingle-step mode, or

[0052] the execution of routines serving for the debugging or emulationof the program-controlled unit by the CPU CPU.

[0053] Furthermore, the OCDS module OCDS can also monitor the occurrenceof the aforementioned or other conditions within the debug resources,more precisely the occurrence of states or events present within theremainder of the debug resources, that is to say, in the exampleconsidered, within the CPU DEBCPU, within the memory device DEBMEM,and/or within the data acquisition device TRACE. Conventional OCDSmodules are not able to do this.

[0054] For the sake of completeness, the OCDS module also could monitorany other debug resource components in addition to the aforementioneddebug resource components or instead of the latter. Independently ofthis, it might be provided that the operations proceeding within thedebug resources could also be monitored by a dedicated (second) OCDSmodule, which is connected via the abovementioned JTAG interface JTAG ora dedicated JTAG interface or some other interface to the abovementionedexternal device or another external device. In this case, the secondOCDS module could even also track the operations proceeding in the firstOCDS module.

[0055] As a result, it is possible that the operations proceeding withinthe debug resources can also be tracked, that is, the debug resourcesthemselves can also be emulated and debugged. Thus, errors that occurwithin the debug resources can also be localized and eliminated.

[0056] Furthermore, the OCDS module OCDS also controls the CPU DEBCPUand the data acquisition device TRACE, and can also be controlled, forits part, by the CPU DEBCPU.

[0057] In the example considered, the data acquisition device TRACE is aNEXUS module, and serves for acquiring, compressing, and outputtingso-called trace information items. The NEXUS module monitors theoccurrence of conditions within the program-controlled unit. Theconditions are prescribed by the OCDS module OCDS or the CPU DEBCPU, andoutputs, if the condition or one of the conditions is met, withoutinterruption to the operation of the program-controlled unit, addresses,data, and/or control signals that are prescribed by the OCDS module OCDSor the CPU DEBCPU, are used or generated within the program-controlledunit and are not accessible from outside the program-controlled unitwithout the debug resources. As a result, it is possible, by way ofexample, but not exclusively by a long way, for the NEXUS module,whenever the CPU CPU would like to read data from a specific address ora specific address range, to output the data fed in response to the CPUCPU.

[0058] The NEXUS module is based on the standard that was defined in1999 by the IEEE Industry Standards and Technology Organization(IEEE-ISTO) and is referred to as “The Nexus 5001 Forum Standard for aGlobal Embedded Processor Debug Interface”. Therefore, with regard tofurther details in respect of the NEXUS module used in the present case,reference is made to this standard.

[0059] The data acquisition device TRACE need not be realized by a NEXUSmodule. What is important, however, is that the data acquisition deviceTRACE does not output in each case all of the addresses, data andcontrol signals to which it has access, but rather outputs only aportion thereof, which is prescribed by the CPU DEBCPU or the OCDSmodule OCDS, and/or only outputs the prescribed or all addresses, data,and control signals if specific conditions are met, for example if andas long as the CPU CPU executes a specific routine, which can beascertained for example from the addresses from which the CPU CPUfetches the instructions that it executes.

[0060] This relieves the burden on the CPU DEBCPU (described in moredetail later) to which the data acquisition device TRACE outputs thedata to be output by it. Provided that the CPU DEBCPU is correspondinglypowerful, the data acquisition device TRACE could be dispensed with,however.

[0061] As just mentioned, the data acquisition device TRACE outputs thedata to be output by it to the CPU DEBCPU.

[0062] The CPU DEBCPU reads from the memory device DEBMEM instructionsand operands stored therein, and executes them. It proves to beadvantageous if the data stored in the memory device DEBMEM can bewritten to the memory device DEBMEM from the external device which isprovided outside the program-controlled unit and cooperates with thedebug resources. The CPU DEBCPU is controlled by the OCDS module OCDS.By outputting corresponding control signals or operands to the CPUDEBCPU, the OCDS module can influence the operations executed by the CPUDEBCPU; the OCDS module can also stop or reset the CPU DEBCPU.

[0063] In the example considered, it is incumbent on the CPU DEBCPU tofilter out a specific portion from the data fed to it by the dataacquisition device TRACE, and to output only these data from theprogram-controlled unit to the external device, the outputting beingeffected via the USB controller USB in the example considered.

[0064] Conventional data acquisition devices (NEXUS modules) output thedata acquired by them—if appropriate after buffer-storage of the data ina memory device provided within the program-controlled unit—immediatelyfrom the program-controlled unit.

[0065] By virtue of the fact that, in the present case, the dataacquisition device TRACE outputs the data acquired by it to the CPUDEBCPU, and the TRACE information items are output to the externaldevice by the CPU DEBCPU, the volume of data output from theprogram-controlled unit can be considerably reduced.

[0066] Reduction of the volume of data is possible inter alia becausethe CPU DEBCPU is able to check the presence of further conditions whichmust be met in order that data are output, and/or because the CPU DEBCPUis able to vary the scope of the addresses, data and/or control signalsto be output depending on the condition met.

[0067] Although this would also be possible, in principle, by using thedata acquisition device TRACE, this would nevertheless require, if evenonly approximately the flexibility which can be obtained by the use ofthe CPU DEBCPU is intended to be achieved in this case, a very extensivelogic or complicated configuration thereof.

[0068] By contrast, the CPU DEBCPU can be realized more simply, and theCPU DEBCPU, even when a very simple CPU with a limited functional scopeis involved, nevertheless has a greater number of possibilities foroptimally adapting to the respective requirements the conditions whichmust be met for outputting of trace information items, and also thescope of the trace information items that are to be output in each case.

[0069] Furthermore, it may also be provided that the CPU DEBCPU checksthe conditions which are checked by the OCDS module in conventionaldebug resources, and/or executes or instigates actions which areinstigated by the OCDS module in conventional debug resources. As aresult, the tasks to be performed by the OCDS module would be limited tothe initialization and/or the control of the remaining debug resourcecomponents, and even these tasks can likewise be executed, at least inpart, by the CPU DEBCPU.

[0070]FIG. 2 shows a configuration corresponding to theprogram-controlled unit in accordance with FIG. 1. In contrast to theconfiguration shown in FIG. 1, the configuration shown in FIG. 2includes two chips, namely a first chip μC and a second chip EC.

[0071] The first chip μC is a microcontroller having no or only verysimple debug resources, and the second chip EC is an emulation chipcontaining the debug resources described above.

[0072] The first chip μC and the second chip EC are soldered one on topof the other using the flip-chip method or are connected to one anotherin some other way, and then form a unit corresponding to theprogram-controlled unit in accordance with FIG. 1.

[0073] However, the first chip μC can also be used without the secondchip EC. Although in that case, for lack of corresponding debugresources, it cannot be debugged or emulated as simply and ascomprehensively as is the case with a multichip module also containingthe second chip EC and with the program-controlled unit in accordancewith FIG. 1, in return, with an otherwise identical performance, it issmaller and less expensive, and consequently better suited to use inmass-produced products.

[0074] The first chip μC contains a CPU CPU, a memory device MEM, afirst I/O controller IO1, a second I/O controller IO2, and an OCDSmodule OCDS1.

[0075] The aforementioned components are connected to one another via abus BUS and/or via individual connections as shown in FIG. 2.

[0076] The CPU CPU, the memory device MEM, and the I/O controllers IO1and IO2 correspond to the components of the program-controlled unit inaccordance with FIG. 1 that are designated by these reference symbols.

[0077] The OCDS module OCDS1 corresponds to a portion of the OCDS moduleOCDS of the program-controlled unit in accordance with FIG. 1 andcorresponds, together with an OCDS module OCDS2 contained in the secondchip EC, to the OCDS module OCDS of the program-controlled unit inaccordance with FIG. 1

[0078] The second chip EC contains debug resources for debugging oremulating the first chip μC, the debug resources containing the OCDSmodule OCDS2 already mentioned above, a CPU DEBCPU, a memory deviceDEBMEM, a data acquisition device TRACE, a USB controller USB, and aninterface SS.

[0079] The CPU DEBCPU, the memory device DEBMEM, the data acquisitiondevice TRACE, and the USB controller USB correspond to the components ofthe program-controlled unit in accordance with FIG. 1 that aredesignated by these reference symbols.

[0080] In normal operation of the program-controlled unit, the CPU CPUreads from the memory device MEM instructions and operands storedtherein, and executes them in interaction with the I/O controllers IO1,IO2, and/or other peripheral units contained in the first chip μC.

[0081] The debug resources, i.e. the OCDS module OCDS1, and the secondchip μC are inactive in normal operation of the program-controlled unit,and are only used during the debugging or emulation of theprogram-controlled unit.

[0082] The debug resources are controlled by a device provided outsidethe program-controlled unit, which may be a computer, for example.

[0083] For this purpose, the external device may be connected accordingto the following:

[0084] via a JTAG interface JTAG1 or some other interface of the chip μCto the debug resources of the chip μC, more precisely to the OCDS moduleOCDS1, and/or

[0085] via a JTAG interface JTAG2 or some other interface of the chip ECto a portion of the debug resources of the chip EC, more precisely tothe OCDS module OCDS2,

[0086] in which case the chip μC can be debugged or emulated via theconnection to the OCDS module OCDS1, and in which case the remainingdebug resource components, that is to say, in particular, the CPUDEBCPU, but also the memory device DEBMEM, the data acquisition deviceTRACE, the USB controller USB, and the OCDS module OCDS1 or a partthereof can be debugged or emulated via the connection to the OCDSmodule OCDS2.

[0087] Via the JTAG interfaces JTAG1 and JTAG2, the chips μC and EC alsooutput specific data to the external device, which can determinetherefrom the operations proceeding in the program-controlled unit.

[0088] In addition to the OCDS module OCDS1, the CPU DEBCPU, the memorydevice DEBMEM, the data acquisition device TRACE, and the USB controllerUSB participate in the debugging or emulation of the chip μC; the OCDSmodule OCDS1 is connected to the aforementioned components via theinterface SS of the chip EC. The construction, the function, and thecooperation of the debug resource components that participate in thedebugging or emulation of the chip μC do not differ or at any rate donot differ significantly from the construction, function, andcooperation of the debug resource components that participate in thedebugging or emulation of the program-controlled unit in accordance withFIG. 1. The connections of the debug resource components among oneanother and to the unit to be debugged or emulated are also identical.Therefore, with regard to the details concerning the construction, thefunction, and the cooperation of the debug resource components whichparticipate in the debugging or emulation of the chip μC, reference ismade to the description of the corresponding components of theprogram-controlled unit in accordance with FIG. 1. All that is differentis that the debug resource components provided for the debugging oremulation of the chip μC are accommodated in part in a dedicated chip(the chip EC).

[0089] Only the OCDS module OCDS2 participates in the debugging oremulation of the debug resources. The module corresponds, apart from itsuse, more precisely to the use for debugging or emulation of debugresources, to a conventional OCDS module. However, the debug resourceswhich are provided for the debugging or emulation of the debug resourcesby which the chip μC can be debugged or emulated can also be constructedlike the debug resources for the debugging or emulation of the chip μC,that is to say, in particular, likewise contain a CPU and/or a dataacquisition device TRACE.

[0090] The debug resources of the program-controlled units describedmake it possible, independently of the details of the practicalrealization, for errors occurring in program-controlled units to belocalized and eliminated under all circumstances rapidly and simply.

We claim:
 1. A program-controlled unit, comprising: debug resourcesincluding a CPU, said debug resources monitoring operations.
 2. Theprogram-controlled unit according to claim 1, wherein said CPU executesactions defined by an external device.
 3. The program-controlled unitaccording to claim 2, wherein said debug resources have a memory devicefor storing instructions to be executed by said CPU and provided by theexternal device.
 4. The program-controlled unit according to claim 2,wherein said debug resources have a memory device storing instructionsto be executed by said CPU upon instigation by the external device. 5.The program-controlled unit according to claim 2, wherein the externaldevice influences a sequence of the actions to be executed by the CPU.6. The program-controlled unit according to claim 2, wherein theexternal device instigates a change in a sequence of the actions to beexecuted by the CPU.
 7. The program-controlled unit according to claim1, wherein said CPU executes instructions determining if conditions haveoccurred, the conditions being selected from the group consisting ofspecific states and events.
 8. The program-controlled unit according toclaim 7, wherein said CPU instigates specific actions when at least oneof the conditions have been met.
 9. The program-controlled unitaccording to claim 8, wherein the specific actions include outputtingspecific data to the external device.
 10. The program-controlled unitaccording to claim 8, wherein the specific actions include outputtingspecific trace information items to the external device.
 11. Theprogram-controlled unit according to claim 10, wherein said CPU is fed aportion of the trace information items and selects the specific traceinformation items for outputting from the trace information, items. 12.The program-controlled unit according to claim 11, further comprising adata acquisition device selecting a specific portion of the traceinformation items and feeding the specific portion of the traceinformation items to said CPU.
 13. The program-controlled unit accordingto claim 12, wherein said data acquisition device is a NEXUS module. 14.The program-controlled unit according to claim 1, wherein said CPUcontrols at least an additional portion of the debug resources.
 15. Theprogram-controlled unit according to claim 1, wherein: said debugresources are divided into two portions, and a first of said twoportions monitors operations proceeding within a second of said twoportions.
 16. The program-controlled unit according to claim 15, whereinsaid first portion of said debug resources monitors the occurrence ofspecific conditions within said second portion of said debug resourcesand executes specific actions when at least one of the specificconditions occurs.
 17. The program-controlled unit according to claim15, wherein said first portion of said debug resources is an OCDSmodule.
 18. A program-controlled unit, comprising: debug resourcesdivided into a portion and a remainder, said remainder having operationsproceeding therein, and said portion monitoring the operationsproceeding within said remainder.
 19. The program-controlled unitaccording to claim 18, wherein said portion of said debug resourcesmonitoring the operations proceeding within said debug resourcesmonitors occurrence of specific conditions within said debug resourcesand executes specific actions when at least one of said conditionsoccur.
 20. The program-controlled unit according to claim 18, whereinsaid portion of said debug resources monitoring the operationsproceeding within said debug resources is an OCDS module.
 21. Theprogram-controlled unit according to claim 18, wherein said debugresources include a CPU.
 22. The program-controlled unit according toclaim 21, wherein said CPU executes actions defined by an externaldevice.
 23. The program-controlled unit according to claim 22, whereinsaid debug resources include a memory device for storing instructions tobe executed by said CPU, said memory device being written to by theexternal device.
 24. The program-controlled unit according to claim 22,wherein said debug resources include a memory device for storinginstructions to be executed by said CPU, said memory device beingwritten to upon instigation by the external device.
 25. Theprogram-controlled unit according to claim 22, wherein said CPU executesa sequence of a program, the sequence being influenced by the externaldevice.
 26. The program-controlled unit according to claim 22, whereinsaid CPU executes a sequence of a program, the sequence being influencedupon instigation by the external device.
 27. The program-controlled unitaccording to claim 21, wherein said CPU executes instructionsdetermining if conditions have occurred, the conditions being selectedfrom the group consisting of specific states and events.
 28. Theprogram-controlled unit according to claim 27, wherein said CPU executesfurther instructions instigating specific actions when the conditionsoccur.
 29. The program-controlled unit according to claim 28, whereinthe specific actions include outputting specific data to the externaldevice.
 30. The program-controlled unit according to claim 28, whereinthe specific actions include outputting specific trace information itemsto the external device.
 31. The program-controlled unit according toclaim 30, wherein said CPU is fed a portion of outputtable traceinformation items, selects appropriate portions of the outputtable traceinformation, and outputs the appropriate portions of the outputtabletrace information.
 32. The program-controlled unit according to claim31, further comprising a data acquisition device originating the traceinformation items being fed to the CPU, selecting a specific portion ofthe trace information items as the outputtable trace information itemswhich could be output from the program-controlled unit, and feeding theoutputtable trace information items to said CPU.
 33. Theprogram-controlled unit according to claim 32, wherein said dataacquisition device is a NEXUS module.
 34. The program-controlled unitaccording claim 21, wherein said CPU controls at least a portion of saidremainder.
 35. In a program-controlled unit including debug resourcesfor monitoring operations proceeding within the program-controlled unit,the improvement which comprises: a CPU included in the debug resources.